1. Field of the Invention
The present invention relates to maintaining the structure of viscous materials applied to semiconductor components. More particularly, the present invention relates to inverting electrical components formed from viscous materials or which include viscous materials in order to maintain the material boundary definition during baking, curing, and/or drying.
2. State of the Art
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are goals of the computer industry. As components become smaller and smaller, tolerances for all semiconductor structures (circuitry traces, printed circuit board and flip chip bumps, adhesive structures for lead attachment, encapsulation structures, and the like) become more and more stringent. However, because of the characteristics of the materials (generally viscous materials) used in forming the semiconductor structures, it is becoming difficult to form smaller circuitry traces, conductive polymer bumps with closer pitches, adequate adhesive structures for leads attachment, and adequate encapsulation structures.
U.S. Pat. No. 5,286,679 issued Feb. 15, 1994 to Farnworth et al. ("the '679 patent"), assigned to the assignee of the present invention and hereby incorporated herein by reference, teaches attaching leads to a semiconductor device with adhesive in a "lead-over-chip" ("LOC") configuration. The '679 patent teaches applying a patterned thermoplastic or thermoset adhesive layer to a semiconductor wafer. The adhesive layer is patterned to keep the "streets" on the semiconductor wafer clear of adhesive for saw cutting and to keep the wire bonding pads on the individual dice clear of adhesive for wire bonding. Patterning of the adhesive layer is generally accomplished by hot or cold screen/stencil printing or dispensing by roll-on. Following the printing and baking of the adhesive layer on the semiconductor wafer, the individual dice are singulated from the semiconductor wafer. During packaging, each adhesive coated die is attached to leadfingers of a lead frame by heating the adhesive layer and pressing the leadfingers onto the adhesive. If the adhesive layer is formed of a thermoset material, a separate oven cure is required. Furthermore, the adhesive layer may be formulated to function as an additional passivating/insulating layer or alpha barrier for protecting the packaged die.
Although the teaching of the '679 patent is a substantial advancement over previous methods for attaching leads in a LOC configuration, the miniaturization of the circuitry makes it difficult to achieve an adequate profile on the adhesive, such that there is sufficient area on the top of the adhesive to attach the leadfingers. The process disclosed in the '679 patent is illustrated in FIGS. 23-29. FIG. 23 illustrates a side, cross-sectional view of a semiconductor substrate 602 with a bond pad 604, wherein a stencil or a screen print template 606 has been placed over the semiconductor substrate 602. The semiconductor substrate 602 is generally a wafer, although the term as used herein is not so restricted, and other substrate structures including silicon-on-insulator ("SOI") and printed circuit boards ("PCB") are specifically included. The stencil or screen print template 606 is patterned to clear the area around the bond pads 604 and to clear street areas 608 for saw cutting (i.e., for singulating the substrate into individual dice). An adhesive material 610 is applied to the stencil or screen print template 606, as shown in FIG. 24. Ideally, when the stencil or screen print template 606 is removed, adhesive prints 612 are formed with vertical sidewalls 614 and an adhesive material upper surface 616, as shown in FIG. 25. However, since the adhesive material 610 must have sufficiently low viscosity to flow and fill the stencil or screen print template 606, as well as allow for the removal of the stencil or screen print template 606 without the adhesive material 610 sticking thereto, the adhesive material 610 of the adhesive prints 612 will spread, sag, or flow laterally under the force of gravity after the removal of the stencil or screen print template 606, as shown in FIG. 26. This post-application flow of adhesive material 610 can potentially cover all or a portion of the bond pads 604 or interfere with the singulating of the semiconductor wafer by flowing into the street areas 608.
Furthermore, and of even greater potential consequence than bond pad or street interference is the effect that the lateral flow or spread of adhesive material 610 has on the adhesive material upper surface 616. As shown in FIG. 27, the adhesive material upper surface 616 is the contact area for leadfingers 618 of a lead frame 620. The gravity-induced flow of the adhesive material 610 causes the once relatively well-defined edges 622 of the adhesive material to curve, resulting in a loss of surface area 624 (ideal shape shown in shadow) for the leadfingers 618 to attach. This loss of surface area 624 is particularly problematical for the adhesive material upper surface 616 at the adhesive material end 626 thereof. At the adhesive material end 626, the adhesive material flows in three directions (to both sides as well as longitudinally), causing a severe curvature 628, as shown in FIGS. 28 and 29. Stated are three ways the longitudinal ends of the adhesive print on patch flow in a 180.degree. flow front resulting in blurring of the print boundaries into a curved perimeter. This curvature 628 results in complete or near complete loss of effective surface area on the adhesive material upper surface 616 for adhering the outermost leadfinger closest to the adhesive material end 626 (leadfinger 630). This results in what is known as a "dangling lead." Since the leadfinger 630 is not adequately attached to the adhesive material end 626, the leadfinger 630 will move or bounce when a wirebonding apparatus (not shown) attempts to attach a bond wire (not shown) between the leadfinger 630 and its respective bond pad 604 (shown from the side in FIG. 28). This movement can cause inadequate bonding or non-bonding between the bond wire and the leadfinger 630, resulting in the failure of the component due to a defective electrical connection.
LOC attachment can also be achieved by placing adhesive material on the leadfingers of the lead frame rather than on the semiconductor substrate. The adhesive material 702 is generally spray applied on an attachment surface 704 of leadfingers 706, as shown in FIG. 30. However, the viscous nature of the adhesive material 702 results in the adhesive material 702 flowing down the sides 708 of the leadfinger 706 and collecting on the reverse, bond wire surface 710 of the leadfinger 706, as shown in FIG. 31. The adhesive material 702, which collects and cures on the bond wire surface 710, interferes with subsequent wirebonding which can result in a failure of the semiconductor component. The flow of adhesive material 702 from the attachment surface 704 to the bond wire surface 710 can be exacerbated if the leadfingers 706 are formed by a stamping process, rather than by etching, the other widely employed alternative. The stamping process leaves a slight curvature 712 to edges 714 of at least one surface of the leadfinger 706, as shown in FIG. 32. If an edge curvature 712 is proximate the leadfinger attachment surface 704, the edge curvature 712 results in less resistance (i.e., less surface tension) to the flow of the adhesive material 702. This, of course, results in the potential for a greater amount of adhesive material 702 to flow to the bond wire surface 710.
Material flow problems also exist in application of encapsulation materials. After a semiconductor device is attached to a printed circuit board ("PCB") by any known chip-on-board ("COB") technique, the semiconductor device is usually encapsulated with a viscous liquid or gel insulative material (e.g., silicones, polyimides, epoxies, plastic, and the like). This encapsulation (depending on its formulation) allows the semiconductor device to better withstand exposure to a wide variety of environmental conditions such as moisture, ions, heat and abrasion.
One technique used in the industry is illustrated in FIGS. 33-35. A stencil 802 is placed on a conductor-carrying substrate or PCB 804 such that an open area or stencil cavity 806 in the stencil 802 exposes a semiconductor device 808 to be encapsulated and a portion of the substrate or PCB 804 surrounding the semiconductor device 808, as shown in FIG. 33. An encapsulant material 810 is then extruded from a nozzle 812 into the stencil cavity 806, as shown in FIG. 34. However, when the stencil 802 is removed, the encapsulant material 810 sags or flows laterally under the force of gravity, as shown in FIG. 35. This flowing thins the encapsulant material 810 on the top surface 814 of the semiconductor device 808, which may result in inadequate protection for the semiconductor device 808. Using a thicker encapsulant material would help minimize the amount of flow; however, thicker encapsulant materials are difficult to extrude through a nozzle and are subject to the formation of voids/air pockets. These voids/air pockets can cause delamination from the PCB 804 or the semiconductor device 808, and if the voids/air pockets contain water condensation, during subsequent processing steps the encapsulant material can be heated to the point at which the condensed water vaporizes, causing what is known as a "popcom effect" (i.e., a small explosion) which damages (i.e., cracks) the encapsulation material, resulting in at least contamination and usually irreparable damage, effectively destroying the semiconductor device. Furthermore, using encapsulant materials with high thixotropic indexes may result in a concave shape which thins the encapsulant material 810 on the top surface 814 of the semiconductor device 808, which may result in inadequate protection for the semiconductor device 808, as shown in FIG. 36.
In an effort to cope with the encapsulant flow problem, the damming technique shown in FIGS. 37-40 has been used. A high viscosity material 902 is extruded through a nozzle 904 directly onto a substrate or PCB 906 to form a dam 908 around a semiconductor device 910, as shown in FIG. 37, or a stencil 912 can be placed on the substrate and PCB 906, such that a continuous aperture 914 in the stencil 912 exposes an area around the semiconductor device 910 to be dammed, as shown in FIG. 38. The high viscosity material 902 is then disposed in the stencil aperture 914 to form the dam 908. A low viscosity encapsulation material 916 is then extruded into the area bounded by the dam 908 by a second nozzle 918, as shown in FIG. 39. The dam 908 prevents the low viscosity encapsulation material 916 from flowing, to form the dammed encapsulated structure 920 shown in FIG. 40 after curing. The dam 908 can be made with high viscosity material without adverse consequences since it does not directly contact the semiconductor device 910 or form any part, other than a damming function, of the encapsulation of the semiconductor device 910. Although this damming technique is an effective means of containing the low viscosity encapsulation material 916, it requires additional processing steps and additional equipment, which increase the cost of the component.
Material flow problems further exist in forming conductive line and trace materials. As discussed in Liang et al., "Effect of Surface Energies on Screen Printing Resolution," IEEE Transactions on Components, Packaging, and Manufacturing Technology--Part B, Vol. 19, No. 2, May 1996 ("the Liang article"), miniaturization of semiconductor packages results in increased circuit densities which require a proportionate reduction of the width of printed lines and traces on semiconductor substrates. However, there are two conflicting requirements for the conductive material applied in screen printing the printed lines and traces. The first requirement is that the conductive material should have sufficiently low viscosity to remove mesh marks and surface imperfections induced during the printing process. The conflicting requirement is that the conductive material should be sufficiently high in viscosity such that it does not flow excessively (i.e., spread). If the conductive material spreads, parallel lines could contact one another, resulting in a short. The Liang article investigates the influences of surface energies of the substrates and the conductive material on screen printing resolution. The conclusion of the Liang article is to use substrates with low surface energies, such as polymer-based substrates, to decrease the wettability of the conductive material to improve screen printing resolution. However, this approach limits the flexibility of using different substrate material for applications demanding different performance parameters. Furthermore, using polymer-based substrates may not be acceptable in certain applications such as high surface energy ceramic substrate.
Material flow problems further exist in forming conductive bumps on printed circuit boards and flip chips. Solder bumps, also termed "C4" bumps, for Controlled Collapse Chip Connection, are a conventional means for attaching and forming an electrical communication between a flip chip and a substrate or PCB, wherein the solder bumps are formed on the flip chip as a mirror-image of the connecting bond pads on the PCB, or vice versa. The flip chip is bonded to the PCB by reflowing the solder bumps.
State-of-the-art solder bumps are generally made of multiple layers of various metals or metal alloys (e.g., lead, tin, copper), which will achieve an effective, strong and controlled-boundary bond between the substrate/PCB and the flip chip. However, the formation of these layered solder bumps requires a substantial number of processing steps which increase the cost of the component. Furthermore, the solder bumps require a high temperature to reflow during the attachment of the flip chip to the substrate/PCB, which may damage temperature-sensitive components on the semiconductor device. Thus, solder bumps are being replaced by conductive polymer bumps.
As shown in FIG. 43, conductive polymer bumps 1002 are formed on bond pads 1004 on a semiconductor device substrate 1006. Alternatively, the bumps may be applied to a carrier substrate, such as a PCB. The bond pads 1004 are in electrical communication with circuitry (not shown) on or in the semiconductor substrate 1006 via electrical traces 1008 (shown in shadow) in or on the semiconductor substrate 1006. The conductive polymer bumps 1002 are generally formed either by screen printing or stenciling. As shown in FIG. 41, a print screen or stencil 1010 is placed over the semiconductor substrate 1006 with openings 1012 over and aligned with each bond pad 1004. A conductive polymer 1007 is deposited in the openings 1012, as shown in FIG. 42. The print screen or stencil 1010 is then removed to form the conductive polymer bumps 1002, as shown in FIG. 43. The conductive polymer bumps 1002 are generally made from material which is sufficiently viscous that minimal material flow occurs when the print screen or stencil 1010 is removed. However, this self-minimization of flow is only applicable to specific limited ratios of height to width of the conductive polymer bumps 1002. If the height of the conductive polymer bump 1002 is too great relative to the width, the weight of the conductive material will cause the conductive polymer bump 1002 to collapse on itself and flow laterally. Thus, height-to-width ratios approaching the preferred target of 3:1 or greater obtainable with solder bumps are unattainable with present methods. In short, to attain a satisfactory height of the conductive polymer bump 1002, the width of the conductive polymer bump 1002 must be increased proportionately. However, when the conductive polymer bump 1002 width is increased, for a given minimum pitch in spacing between adjacent conductive polymer bumps 1002 bond pad pitch also increases, which takes up more space on the semiconductor substrate 1006, limiting the number and arrangement of the die-to-carrier substrate connections. This is, of course, in conflict with the goal of miniaturizing semiconductor devices of ever-increasing circuit density.
Thus, it can be appreciated that it would be advantageous to develop a technique to control viscous material flow in the formation of semiconductor components while using commercially-available, widely-practiced semiconductor device fabrication techniques.